Networks on Chip (NoCs) constitute a communication paradigm that scales both in performance and size and is thus suited for chips with 64 or more processor cores. Since NoCs offer a vast design space, fast simulation algorithms are an invaluable tool to ensure that design constraints are met and time to market is short. Although such many core systems have an inherent regular structure, simple parallel simulation algorithms fail to leverage the power of modern simulation machines. Imbalances in the simulated communication leads to imbalances in the workload for the simulator, which simple approaches cannot compensate. This dissertation proposes a parallel simulation approach for Networks on Chips (NoCs) called Task-Based Simulation that achieves high simulation performance while maintaining cycle level accuracy. This is achieved by decomposing the simulation by space and time, which allows decoupling the simulation of consecutive cycles. Task-based simulation achieves speedups that are 1.5 to 2.4 times higher than those of the state of the art. And with overall speedups of up to 23.7x, task-based simulation provides cycle-accurate NoC simulation that is truly scalable.